1. Field of the Invention
The field of the invention relates to data processing and in particular to memory storage cells.
2. Description of the Prior Art
Memory storage cells formed from semiconductors in integrated circuits are known. They are conventionally formed of bistable circuits that can be flipped between one of two stable states. If the circuits are well balanced then they do not preferentially store either state. A well balanced cell that does not preferentially store a particular value will have the advantage of holding either value with approximately the same power loss and will be as easy to write a “one” to as it is to write a “zero”. However, a potential drawback of such a cell is that on power up it is unknown which value will to be stored in these cells and there are circumstances where it would be advantageous to initialise a memory in a known state.
There is a continual demand to reduce the size and power consumption of such memory storage cells. However, with decreasing size, read and write operations which make conflicting demands, may no longer both be successful due to variable threshold voltages of the devices used caused by increasing process variations at the smaller geometries or technology nodes. This is particularly the case where a wide range of voltage, temperature or process limits are used. To extend the range of the cell and enable writes to be performed consistently a write assist signal has been introduced which is used to help flip the cell in cases where the high voltage rail VDD and pull up device hold the node at the input to the cell at too strong a value for the data input to be able to flip the cell to its new state.
One known write assist system uses two power supply rails connected by respective gates to each memory cell to be written. A first of these power supplies is used to power the memory cell in modes other than a write mode and utilises a relatively high supply voltage level. The second power supply has a lower voltage level and is used during write operations to power the memory cell. The lower supply voltage used during such write operations enables the memory cell to be more readily written. A disadvantage with this approach is that although it improves the writing of a zero and increases the pulldown speed for this write it slows the writing of the one. It also requires two separate power rails to be routed through the memory.
Another known approach to providing a write assist mechanism is using the memory cell with a gated power supply from a single source. When operating other than to perform a write, the memory cell is supplied with power through the gate. When it is desired to write to that memory cell, the gate isolates the memory cell from the power supply such that the memory cell is unpowered during the write operation. This makes it easier for a new data value to be written into the memory cell. Memory cells are not normally provided with individually controllable power supplies since this would consume a disadvantageous number of gates and reduce the memory density. Rather, a group of memory cells usually share a power supply line, which may be a virtual power supply line separated by a gate from a permanently powered power supply line in accordance with this technique. However, when multiple memory cells share a power supply in this way, all of these memory cells will be isolated from the power supply and be unpowered whilst one of the memory cells is being written. This will leave the unpowered memory cells vulnerable to data loss. This risk is increased when one considers manufacturing and process variations which can occur rendering individual memory cells particularly vulnerable to data loss when unpowered. This approach suffers from the disadvantage of potentially rendering a memory unreliable. Furthermore, as for the previous example it suffers from the disadvantage of improving the speed for writing a zero but slowing the writing of a one.
A further write assist method is disclosed in U.S. Ser. No. 11/392,961 the entire contents of which are incorporated herein by reference. In accordance with this technique a memory cell is provided with power via a power supply control circuit including at least two gates which are switched by a write assist signal to provide either a low resistance or high resistance path through the power supply control circuit. Thus, the memory cell is always powered and connected to the power supply, but when the high resistance path is in use during writing to the memory cell, then this will effectively weaken the power supply to the memory cell such that it is easier for a new data value being written into that memory cell, i.e. to change the state of the memory cell and overcome the inherent stability in the memory cell which tends to oppose changes in its state. Once again this suffers from the problem of increasing the speed of writing a zero, but decreasing performance for writing a one.